Semiconductor device, production method and production device thereof

ABSTRACT

The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film  103  allow the metal elements to be diffused into the base silicon oxide film  103  to thereby form an insulating film structure  105  as a gate insulating film, after forming the base silicon oxide film  103  on a surface of a silicon substrate  101 . The insulating film structure  105  including a silicate region comprises a silicon oxide film region, a silicate region, and a metal rich region, forming a silicate structure having composition modulation in which composition of metal increases as closer to an upper portion, and the composition of silicon increases as closer to a lower portion.

TECHNICAL FIELD

The present invention relates to a semiconductor device having a highdielectric constant thin film, and manufacturing method andmanufacturing apparatus thereof, more particularly, to a semiconductordevice which provides higher performance and lower power consumption ofa gate insulating film which constitutes an MOSFET(Metal-Oxide-Semiconductor Field Effect Transistor), and manufacturingmethod and manufacturing apparatus thereof.

BACKGROUND OF THE ART

Silicon oxide films have process stability and excellent electricalinsulation, and are being used for gate insulating materials of anMOSFET. With device miniaturization in recent years, thinning of a gateinsulating film has been increasingly growing, and a device with a gatelength of 100 nm or less requires a thickness of a silicon oxide filmwhich is the gate insulating film, to be 1.5 nm or less from arequirement of the scaling law. However, if such an ultra-thininsulating film is used, upon applying gate bias voltage to a gateelectrode, the magnitude of tunneling current sandwiched between a gateinsulating layer and the gate electrode becomes an unignorable valueagainst source/drain current, and exceeds a permissible range of devicedesign. This would be a big barrier to promoting higher performance andlower power consumption of the MOSFET. Accordingly, research anddevelopment is proceeding with the aim to thin a film thickness of aneffective gate insulating film and to control the tunneling current towithin the permissible values.

One of them is a method of adding nitrogen into a silicon oxide film tothereby increase dielectric constant more than that of a pure siliconoxide film, and to reduce a film thickness of an effective, namely,electrical gate insulating layer without thinning a physical filmthickness. Fabricating techniques of such a silicon oxynitride filminclude a method of making high-temperature heat treatment of thesilicon oxide film in gas containing nitrogen such as ammonia (NH₃) tothereby introduce the nitrogen into the silicon oxide film after formingthe silicon oxide film on a surface of a silicon substrate. However,this method gives rise to a problem that the heat treatment in gasatmosphere causes segregation of the nitrogen into an interface betweenthe silicon oxide film and the silicon substrate to producedeterioration of interface electrical characteristics. In the case of asilicon oxide film, it is generally possible to realize a good qualityjunction with less interface roughness and defect density. However, if asilicon oxynitride film is fabricated by the aforementioned technique,the interface roughness and the interface defect density will beincreased by the segregated nitrogen in the interface.

Therefore, a technology (plasma nitriding technology) in which a siliconoxide film is exposed to nitrogen plasma to selectively nitride asurface side has been studied in recent years. In the technologyapplying this plasma, it is possible to control nitrogen concentrationof an interface to a lower level and to minimize electricalcharacteristic deterioration caused by the aforementioned nitrogen.However, relative dielectric constant of a pure silicon oxynitride filmis only twice as many as that of the silicon oxide film, and higherdielectric constant of an insulating film by nitrogen addition to thesilicon oxide film has limitations. Thus increasing the relativedielectric constant to not less than 10 is impossible in principle.

Accordingly, as the next-generation technology in which the deviceminiaturization is moving ahead, an attempt is further being made toadopt thin film materials with relative dielectric constant of not lessthan 10, or a silicate thin film which is a composite material of thesematerials and silicon as the gate insulating film, in place of thesilicon oxide film or an oxynitride film. As these high dielectricconstant materials, Al₂O₃, ZrO₂, or HfO₂, and rare-earth element oxidessuch as Y₂O₃, and further lanthanoide rare earth element oxides such asLa₂O₃ are being studied as candidate materials. This basis is that thereexists a thickness that use of these high dielectric constant filmswould allow prevention of the tunneling current, while maintainingcapacity of the gate insulating film in accordance with the scaling law,even if the gate length is miniaturized.

Note that assuming that the gate insulating materials are the siliconoxide films regardless of type of the gate insulating film, the filmthickness obtained from back calculation of gate capacity is calledSilicon Effective Oxide Thickness. More specifically, letting therelative dielectric constant of the insulating film and the relativedielectric constant of the silicon oxide film eh and eo, respectively,and the thickness of the insulating film dh, the Silicon Effective OxideThickness makes de=dh (eo/eh). This formula indicates that if a materialhaving dielectric constant eh larger than eo is used, even an insulatingfilm having a thick physical film thickness can be effectively andelectrically equivalent to a thin silicon oxide film. The relativedielectric constant eo of the silicon oxide film is approximately 3.9,so that, for example, if a high dielectric film having relativedielectric constant eh=39 which is ten times as high as that is used,even the physical film thickness of the insulating film having athickness of 15 nm will effectively and electrically make the SiliconEffective Oxide Thickness of 1.5 nm, enabling drastic reduction of thetunneling current.

In addition, each of a metal oxide and a silicate thin film features thefollowing. If the metal oxides such as ZrO₂ and HfO₂ are used as a highdielectric constant gate insulating film, higher relative dielectricconstant may be achieved. On the other hand, it is believed thatalthough the relative dielectric constant decreases in a silicatematerial in which silicon is contained, thermal stability is enhanced,as well as the interface electrical characteristics may be improved ascompared with the case where the metal oxides are directly joined ontothe silicon substrate.

As described above, development of the next-generation MOSFET isconsidering to adopt the high dielectric constant thin film as the gateinsulating film materials, and to adopt CVD (Chemical Vapor Deposition)using different kinds of source gas, or ALD (Atomic Layer Chemical VaporDeposition) which controls CVD deposition on an atomic layer basis, asdeposition techniques of the high dielectric constant thin film onto thesurface of the silicon substrate.

In an initial stage of development of the high dielectric constant gateinsulating film, a physical evaporation method such as sputtering,reactive sputtering, or Molecular Beam Deposition has been used with theaim of material search. In these deposition techniques, reported areexamples in which a high dielectric constant film has been directlydeposited on a surface of a silicon substrate, and in which anultra-thin silicon oxide film, to be more precise, with a thickness ofnormally less than 1 nm, has been inserted into an interface between ahigh dielectric constant thin film and the silicon substrate for thepurpose of controlling an early reaction of CVD or ALD deposition, andof improving thermal stability of the interface between the highdielectric constant thin film and the silicon substrate. In the lattercase, the ultra-thin silicon oxide film is formed on the surface of thesilicon substrate, and then the deposition of the high dielectricconstant thin film is carried out by different kinds of depositionmethods. Commonalities in these deposition techniques are thatstoichiometric composition on the surface of the silicon substrate, orthe deposition of the high dielectric constant film in agreement withsilicate composition which is neither too much nor too little in oxygenconcentration is necessary, and in particular, a structural defect suchas an oxygen deficiency in a film causes deterioration of electricalcharacteristics and increase in leakage current.

With respect to various high dielectric constant materials fabricated bythe aforementioned thin film deposition methods, the characteristicshave been studied heretofore. Among these, the biggest technical problemtoward the development of the next-generation MOSFET is improvement inthe interface electrical characteristics between the high dielectricconstant thin film and the silicon substrate. More specifically, theinterface defect density between the high dielectric constant thin filminterface and the silicon substrate is higher by one to two digits thanthe interface defect density between the silicon oxide film and thesilicon substrate, deterioration of the mobility becomes significant dueto charge captured by the interface defect, and current drive capabilityof the MOSFET declines. This cancels out the effect that the gateinsulating film has been thinned.

As for means to improve the interface electrical characteristics, astructure in which the silicon oxide film is inserted into the interfacebetween the high dielectric constant film and the silicon substrate asan interface oxide layer is being studied. An interface structure whichdetermines the electrical characteristics is deeply related to afabrication method of the high dielectric constant thin film. Forexample, even if the high dielectric constant thin film is directlydeposited on the surface of the silicon substrate by means of the CVD orsputtering method, oxidation of the silicon substrate progressesconcurrently with thin film deposition to form an interface layer mainlycomprising the silicon oxide film when an oxidizing agent is introducedduring the deposition, or when a large amount of residual oxygen arepresent within deposition apparatus. It is difficult to independentlycontrol the deposition of these interface layers, thus it beingimpossible to independently design the structure in which the interfaceelectrical characteristics are optimized.

Meanwhile, techniques in which a silicon oxide film is intentionallyinserted as an interface oxide layer include a method of forming anultra-thin silicon oxide film on a surface of a silicon substrate inadvance before depositing a high dielectric constant thin film, and amethod of depositing a high dielectric constant thin film before givingheat treatment to allow growth of the silicon oxide film. The formermethod has an effect that insertion of the silicon oxide film enhancesinterface thermal stability. However, it is considered to be importantthat a film thickness of the ultra-thin silicon oxide film which isformed on the surface of the silicon substrate should be 0.6 nm or lessdue to low relative dielectric constant of the silicon oxide film. Inaddition, an ultra-thin base silicon oxide film is sometimes altered ina process of depositing the high dielectric constant thin film on theultra-thin silicon oxide film, and hence interface characteristicsbetween the ultra-thin silicon oxide film and the silicon substratedeteriorate. The latter method is a method utilizing phenomenon in whichoxygen easily diffuses in the high dielectric constant thin film to forman interface layer. However, in the case where metal elements in thehigh dielectric constant film diffuse into the interface layer in a heattreatment process, it is impossible to form an ideal interface betweenthe silicon oxide film and the silicon substrate excellent in theelectrical characteristics.

In this way, the prior art had the problems that although in order toimprove the interface electrical characteristics of the gate insulatingfilm having high dielectric constant, formation of the high dielectricconstant thin film excellent in film quality was necessary, whilemaintaining a good quality interface between the silicon oxide film andthe silicon substrate, it was difficult to separate and control aforming process of the interface layer comprising the silicon oxidefilm, and a deposition process of the high dielectric constant film.

DISCLOSURE OF THE INVENTION

It is possible that a film thickness of said cap layer is 1 nm or less.

It is possible that the film thickness of said cap layer is 0.5 nm orless.

It is possible that said insulating film structure has the compositionmodulation in which the composition of silicon in a film thicknessdirection is high in the lowermost portion and uppermost portion and lowin the central portion, in the vicinity of said silicon region.

It is possible that said insulating film structure has the compositionmodulation in which the composition of said at least one metal elementin the film thickness direction is low in the lowermost portion anduppermost portion and high in the central portion, in the vicinity ofsaid silicon region.

It is preferable that Equivalent Oxide Thickness of said insulating filmstructure be smaller than the Equivalent Oxide Thickness of the siliconoxide film into which said at least one metal element is diffused.

It is possible that said silicon oxide constituting said at least onesilicate region is a silicon oxynitride into which nitrogen has beenintroduced.

It is possible that the concentration distribution of said at least onemetal element in said at least one silicate region is distributionderived from the heat treatment under reduced pressure oxygen conditionsbelow atmospheric pressure.

It is possible that said insulating film structure further includes acap region composed of any one of the silicon nitride and the siliconoxynitride.

It is possible that a thickness of said cap region is 0.5 nm or less.

It is possible that said conductive region comprises the gate electrode,and said insulating film structure comprises the gate insulating film,and that a hysteresis width of gate capacity-bias characteristics is 5mV or less by an applied gate bias within device operating voltage

It is possible that said insulating film structure comprises saidsilicate region composed of the silicon oxide containing said at leastone metal element, and the silicon oxide region composed of the siliconoxide not containing said at least one metal element, and that aphysical thickness of said insulating film structure is 3.5 nm or less,the physical thickness of said silicate region being thinner than thephysical thickness of said silicon oxide region.

It is possible that the physical thickness of said silicate region is1.5 nm or less.

It is possible that said conductive region comprises the gate electrode,and said insulating film structure comprises the gate insulating film,the gate electrode having nitride film side walls.

A second aspect of the present invention provides a manufacturing methodof a semiconductor device including an insulating film structure whichelectrically insulates a conductive region from a silicon region, themanufacturing method at least comprising the steps of:

-   -   forming a base silicon oxide film on said silicon region;    -   forming a metal layer on said base silicon oxide film; and    -   giving heat treatment to thereby cause a silicate reaction in an        interface between said base silicon oxide film and said metal        layer to allow at least one thermally diffused metal element        contained in said metal layer into said base silicon oxide film        to thereby form the insulating film structure containing a        silicate region composed of the silicon oxide containing said at        least one metal element thermally diffused into a region of at        least part of said base silicon oxide film.

It is possible to carry out said heat treatment causing said interfacesilicate reaction in reducing atmosphere.

It is possible to carry out said heat treatment causing said interfacesilicate reaction in atmosphere containing any one of hydrogen andammonia.

It is possible that said thermally diffused forms said insulating filmstructure including at least one silicon oxide region composed of thesilicon oxide into which said at least one metal element is not diffusedby said thermal diffusion, at least one metal rich region into whichsaid at least one metal element has been diffused at high concentration,and said at least one silicate region which is located between saidsilicon oxide region and said metal rich region and into which said atleast one metal element has been diffused at concentration lower thanthat of said metal rich region.

It is possible that said silicate region has composition modulation inwhich composition of said at least one metal element increases as closerto said metal rich region and decreases as closer to said silicon oxideregion, and, on the other hand, in which the composition of silicondecreases as closer to said metal rich region and increases as closer tosaid silicon oxide region.

It is possible that said metal rich region comprises a metal oxide notcontaining silicon.

It is possible that said metal rich region comprises a metal richsilicate having higher concentration distribution of said at least onemetal element than that of said silicate region.

It is possible that a process of forming said metal layer comprises adeposition process carried out by setting residual oxygen partialpressure to 1×10⁻⁶ T or less.

It is possible that the deposition process of said metal layer iscarried out by causing temperature rise of said silicon region from roomtemperature.

It is possible to further carry out a nitride treatment processsubsequent to said heat treatment process.

It is possible that said nitride treatment process comprises the heattreatment in ammonia.

It is possible that said nitride treatment process comprises nitrogenplasma treatment.

It is possible that said at least one metal element is at least only anyone of Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb,Dy, Ho, Er, Tm, Yb, and Lu.

It is possible that when said at least one metal element is only Al, asource of the metal element comprises the metal layer abutting on asurface of the base silicon oxide film with a film thickness of not lessthan 0.6 nm, which extends on said silicon region.

It is possible that said at least one metal element contains at leastonly any one of Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu,Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and that the source of the metalelement comprises the metal layer abutting on the surface of the basesilicon oxide film with a film thickness of not less than 1 nm, whichextends on said silicon region.

It is possible that a forming process of said metal layer is a processwhich is carried out on condition that the film thickness of metaldeposition is 1 nm or less.

It is possible that the forming process of said metal layer is a processwhich is carried out on condition that the film thickness of the metaldeposition is 0.6 nm or less.

It is possible that said heat treatment process is carried out for thesilicate reaction in the interface between said metal layer and saidbase silicon oxide film to progress to an upper portion of said metallayer, thereby forming said insulating film structure up to andincluding the uppermost portion from silicate.

When an unreacted metal region is left in said metal layer by said heattreatment process, it is possible to further include a process ofremoving the unreacted metal region subsequent to said heat treatmentprocess.

It is possible that the process of removing said reacted metal region iscarried out by use of a hydrofluoric acid solution or an ammoniaperoxide solution.

It is possible to further include the heat treatment process forreforming film quality subsequent to the process of removing saidreacted metal region.

It is possible to further include a process of depositing a cap layercomposed of a silicon-containing insulating film on said metal layerafter the formation process of said metal layer and before said heattreatment process to thereby allow said silicate reaction to cause thethermal diffusion of said at least one metal element into said basesilicon oxide film and said cap layer to thereby form a first silicatelayer composed of the silicon oxide containing said at least one metalelement thermally diffused in a region of at least part of said basesilicon oxide film, as well as to form a second silicate layer composedof a silicon insulator containing said at least one metal elementthermally diffused in a region of at least part of said cap layer.

It is possible that said cap layer comprises any one of a silicon oxidefilm, a silicon oxynitride film, a silicon nitride film, and at leasttwo laminated structures of these.

It is possible that the film thickness of said cap layer is 1 nm orless.

It is possible that the film thickness of said cap layer is 0.5 nm orless.

It is possible that said insulating film structure has the compositionmodulation in which the composition of silicon in the film thicknessdirection is high in the lowermost portion and uppermost portion and lowin the central portion, in the vicinity of said silicon region.

It is possible that said insulating film structure has the compositionmodulation in which the composition of said at least one metal elementin the film thickness direction is low in the lowermost portion anduppermost portion and high in the central portion, in the vicinity ofsaid silicon region.

It is possible that Equivalent Oxide Thickness of said insulating filmstructure including said silicate region is smaller than the EquivalentOxide Thickness of said base silicon oxide film.

It is possible that said base silicon oxide film comprises a siliconoxynitride film into which nitrogen has been introduced.

It is possible that said heat treatment process is carried out underreduced pressure oxygen conditions below atmospheric pressure.

It is possible that said silicon region comprises a silicon substrate,said conductive region comprises a gate electrode, and said insulatingfilm structure comprises a gate insulating film.

A third aspect of the present invention provides manufacturing apparatusof a semiconductor device having a gate insulating film whichelectrically insulates a gate electrode from a silicon substrate, themanufacturing apparatus comprising:

-   -   a deposition chamber introducing said silicon substrate on which        a base silicon oxide film has been formed;    -   a metal evaporation mechanism by which a metal layer is        deposited on said base silicon oxide film of said silicon        substrate introduced into the deposition chamber; and    -   a vacuum pump controlling residual oxygen partial pressure in        said deposition chamber,    -   wherein said metal evaporation mechanism allows said vacuum pump        to make the residual oxygen partial pressure 1×10−⁶ Torr or less        to deposit said metal layer on said base silicon oxide film.

It is possible that said manufacturing apparatus further includes asubstrate heating mechanism by which said silicon substrate introducedinto said deposition chamber is heated.

It is possible that said metal evaporation mechanism allows a spacingbetween an evaporation source and a substrate to be set to not less than100 mm to deposit said metal layer on said base silicon oxide film.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A to FIG. 1D are longitudinal sectional views in a manufacturingprocess of an insulating film structure comprising a silicate highdielectric constant thin film included in a semiconductor device in oneembodiment according to the present invention.

FIG. 2 is a diagram showing metal element concentration distribution ina film thickness direction of the silicate high dielectric constant thinfilm included in a gate insulating film structure in one embodimentaccording to the present invention.

FIG. 3A is a longitudinal sectional view showing the insulating filmstructure in which an unreacted region is left on an upper portion of ametal layer by an interface reaction between the metal layer and thebase silicon oxide film in FIG. 1C.

FIG. 3B is a longitudinal sectional view showing the insulating filmstructure after removing an upper unreacted region and further carryingout reforming heat treatment shown in FIG. 3A.

FIG. 4 is a diagram for illustrative of a relationship of physical filmthicknesses A and B of the gate insulating film, namely, the physicalfilm thickness A of a metal silicate region containing metal elementsand the physical film thickness B of a silicon oxide region notcontaining metal elements, in the gate insulating film.

FIG. 5 is a partial longitudinal sectional view showing an example of asemiconductor device to which the insulating film structure is appliedaccording to the present invention shown in FIG. 2.

FIG. 6A to FIG. 6D are partial longitudinal sectional views in themanufacturing process of the insulating film structure comprising thesilicate high dielectric constant thin film included in a semiconductordevice in another embodiment according to the present invention.

FIG. 7 is a diagram showing the metal element concentration distributionin the film thickness direction of the silicate high dielectric constantthin film included in the insulating film structure shown in FIG. 6D.

FIG. 8A to FIG. 8D are longitudinal sectional views showing themanufacturing process of a lanthanum silicate high dielectric constantthin film included in a semiconductor device in a first exampleaccording to the present invention.

FIG. 9 is a diagram showing an overview of constitution of vacuumevaporation apparatus used for manufacturing the lanthanum silicate highdielectric constant thin film shown in FIG. 8A to FIG. 8D.

FIG. 10 is a diagram showing the relationship between Equivalent OxideThickness and leakage current found from capacity-voltagecharacteristics and current-voltage characteristics of the lanthanumsilicate high dielectric constant thin film shown in FIG. 8D.

FIG. 11A to FIG. 11D are longitudinal sectional views showing themanufacturing process of a hafnium silicate high dielectric constantthin film included in a semiconductor device of a second exampleaccording to the present invention.

FIG. 12 is a diagram showing an overview of the constitution ofsputter-deposition apparatus used for the manufacturing process of thehafnium silicate high dielectric constant thin film shown in FIG. 11A toFIG. 11D.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings.

FIG. 1A to FIG. 1D are partial longitudinal sectional views in amanufacturing process of an insulating film structure comprising asilicate high dielectric constant thin film included in a semiconductordevice in one embodiment according to the present invention. FIG. 2 is adiagram showing concentration distribution of metal elements in a filmthickness direction of the silicate high dielectric constant thin filmincluded in a gate insulating film structure in one embodiment accordingto the present invention.

In a manufacturing process of a high dielectric constant thin film inthe present embodiment, after giving hydrogen termination treatment to asurface of a silicon substrate 101 shown in FIG. 1A, a base siliconoxide film 103 comprising an oxynitride film is formed, as shown in FIG.1B. As shown in FIG. 1C, metal elements are supplied to the surface ofthe base silicon oxide film to form a metal layer 104. As shown in FIG.1C, an insulating film structure 105 including a silicate region isformed on the silicon substrate 101 by heat treatment. A high dielectricconstant film layer comprising silicate is not directly deposited on thesilicon substrate 101, but the insulating film structure 105 includingthe silicate region is formed on the silicon substrate 101 as a highdielectric constant thin film by causing an interface reaction betweenthe base silicon oxide film 103 and the metal layer 104 by heattreatment.

First, a high quality base silicon oxide film 103 is formed on thesurface of the silicon substrate 101, as shown in FIG. 1B. Note that thesilicon substrate 101 is being given the hydrogen termination treatmentwhich eliminates unstable dangling bonds by binding a surfacetermination hydrogen 102 with remaining valence arms of silicon atoms. Afilm thickness of the base silicon oxide film 103 is preferably setthickly as compared with normally 0.6 nm or less which is a filmthickness of a conventional surface insertion layer, and an electricalfilm thickness of the insulating film structure 105 which is finallyrequired, namely, the base silicon oxide film 103 as thick as EquivalentOxide Thickness is formed. Although detailed description will be givenwith reference to FIG. 2 later, the insulating film structure 105includes a silicate region 105-2 which acts as the high dielectricconstant film into which metal elements are introduced by the interfacereaction, and a silicon oxide region 105-1 into which no metal elementsare introduced.

A formation method of the base silicon oxide film 103 shown in FIG. 1Bneeds no particular limits, but may adopt a known thermal oxide filmformation process as one typical example. In this case, the base siliconoxide film 103 is required to be ultrathin as thin as the EquivalentOxide Thickness of a high dielectric constant gate insulating filmstructure 105 which is finally formed, so that RTO (Rapid ThermalOxidation) is useful. Note that chemical oxide formed by wet processingis capable of easily forming an ultrathin base silicon oxide film 103,but has the possibility to exert little effect in the present inventiondue to inferiority in interface electrical characteristics. Furthermore,from a viewpoint of reducing the Equivalent Oxide Thickness, it isrequired that the film thickness of the base silicon oxide film 103which is formed on the surface of the silicon substrate 101, that is,the film thickness of the base silicon oxide film 103 before theinterface reaction is caused be reduced, as a process shown in FIG. 1B.However, in order to consider that metal elements are diffused into thebase silicon oxide film 103 in a process to be described later, and tomaintain high quality of an interface between the base silicon oxidefilm 103 and the silicon substrate 101, it is preferable that the filmthickness of the base silicon oxide film 103 be normally not less than 1nm. However, when selecting an element in which diffusion of metalelements into the base silicon oxide film 103 is not so noticeable asA1, the film thickness of the base silicon oxide film may be reduced tothe extent of approximately 0.6 nm at minimum.

In addition, it is useful that an oxynitride film in which tracenitrogen, for example, as much as a few percent is introduced into thebase silicon oxide film 103 is used as a base layer. In this case,useful is a structure in which the surface of the base silicon oxidefilm 103 is selectively nitrided by a radical nitriding process suchthat nitrogen is not segregated into the interface.

Next, as shown in FIG. 1C and FIG. 1D, metal elements constitutingsilicate are supplied onto the surface of the base silicon oxide film103, and then the metal elements are diffused into the base siliconoxide film 103 by the heat treatment process carried out either duringor after supplying the metal elements to form a silicate layer 105-2 inwhich silicon oxidation is converted into silicate, in a region exceptfor the vicinity region of the interface with the silicon substrate 101which is part of the base silicon oxide film 103, in particular, on anupper layer portion of the base silicon oxide film 103.

A physical evaporation method such as a CVD chemical method and sputterdeposition is conceivable as a means for supplying the metal elements tothe surface of the base silicon oxide film 103. Particularly,considering that oxidation rate of the metal elements constituting thehigh dielectric constant film is very fast, it is preferable to adopt anultrahigh vacuum sputtering method which is capable of reducing residualoxygen partial pressure in treatment atmosphere during a formationprocess of the metal layer 104 shown in FIG. 1B to 1×10 ⁻⁶ Torr or less.In addition, metal deposition by a sputtering method requires to reducedamage to the base silicon oxide film 103 during the deposition, andoutweighs spacing a distance between a sputter evaporation source andthe silicon substrate 101 and supplying metal on condition that fastions or a large amount of photons do not enter the silicon substrate101. In general, a distance between an evaporation source and asubstrate wafer needs to be not less than 100 mm, and a remote type ofdeposition apparatus having secured a distance of not less than 200 mmis preferable. Furthermore, an ideal method of supplying metal includesa vacuum evaporation method by electron beam heating of metallicmaterials, and the like.

In a process of supplying the metal elements to form the metal layer104, atomospheric gas and a degree of vacuum are important, as describedabove. More specifically, it is difficult to maintain an ideal interfacewith the silicon substrate 101 because in conventional depositionmethods by metal evaporation in oxygen atmosphere, such as reactivesputtering and reactive evaporation, an oxidation reaction progressesalong with supply of the metal elements to form a stoichiometric metaloxide, leading to a progress of the interface reaction from an earlystage of the deposition. However, if the metal elements are suppliedonto the base silicon oxide film 103 of not less than 1 nm which isever-thicker, on condition that the residual oxygen partial pressure is1×10⁻⁶ Torr or less during supplying the metal elements as with thepresent invention, part of the metal elements might come into anoxidized state by an effect of trace residual oxygen, but an interfacestructure between the base silicon oxide film 103 and the siliconsubstrate 101 is well preserved.

In the heat treatment process, the interface reaction is accelerated inan oxidation process of a metal reaction region containing a largeamount of oxygen deficiencies. This makes it possible to effectivelycarry out an interface silicate reaction between the base silicon oxidefilm 103 and the metal layer 104 in the heat treatment process. Forexample, if Zr elements are supplied to the base silicon oxide film 103by use of the vacuum evaporation method on condition that the residualoxygen partial pressure is 1×10⁻⁶ Torr or less, no changes will occur ina state of Si—O bonding in a film of the base silicon oxide film 103,and most of the Zr elements will be oxidized even under theaforementioned residual oxygen partial pressure due to very fastoxidation rate of the Zr elements. However, the fact that a large amountof oxygen deficiencies are present in the metal reaction region, with astructure of disordered atomic arrangement may be confirmed byevaluation methods of X-ray photoelectron spectroscopy and the like,thus making it possible to effectively carry out the interface silicatereaction in the heat treatment process. In contrast with this, if thesupply of the metal elements is carried out on condition that theresidual oxygen partial pressure is higher than 1×10⁻⁶ Torr, the amountsof oxygen deficiencies in the metal reaction region will dramaticallydrop and the interface silicate reaction will be suppressed in the heattreatment process.

Note that only introduction of the metal elements into the base siliconoxide film 103 leads to a silicate structure containing a large amountof oxygen deficiencies, but giving additional reduced pressure oxidationtreatment after the metal diffusion into the base silicon oxide film 103enables the oxygen deficiencies of the silicate layer 105-2 to beeliminated, while maintaining an interface state with the siliconsubstrate 101, because oxygen diffusion in the high dielectric constantthin film such as silicate rapidly progresses as compared with theoxygen diffusion in the base silicon oxide film 103, and furtheroxidation rate of the metal elements is very fast.

On the other hand, the interface between the high dielectric constantthin film such as HfO₂ and ZrO₂ and the silicon substrate 101 isthermally stable. However, if metal elements constituting the silicatelayer 105-2 which is a high dielectric constant film, is supplied ontothe surface of the base silicon oxide film 103, Metal-O bonding which isa bonding of a metal atom with an oxygen atom, is stronger than Si—Obonding, so that silicate bonding (Metal-O—Si) will be formed, and aninterface silicate formation reaction may be driven by temperature riseof the substrate during supplying the metal elements or the heattreatment process after supplying the metal elements. Consequently, theinterface reaction will be accelerated faster than interface oxidationrate through the metallic oxide having stoichiometric film composition.

Meanwhile, in a process of supplying the metal elements to form themetal layer 104, the temperature rise of the silicon substrate 101 isalso effective. Oxidation of the metal layer 104 is likely to progresseven in reduced residual oxygen partial pressure apparatus because ofvery fast oxidation rate of the metal elements. Accordingly, it isuseful to cause the temperature rise of the silicon substrate 101 duringsupplying the metal elements to accelerate a reaction with the basesilicon oxide film 103, namely, metal element diffusion at the same timeas supplying the metal elements. However, even if a temperature of thesilicon substrate 101 is made room temperature, a large amount of theoxygen deficiencies are present in the metal reaction region asdescribed above. Therefore, even if the heat treatment is carried outafter supplying the metal elements, the interface reaction, namely, themetal element diffusion is accelerated.

It is conceivable that conditions for the heat treatment process includea condition under which oxygen partial pressure is reduced with theprimary object of the metal element diffusion, and a condition underwhich atmosphere contains oxygen with the primary object of oxygendeficiency reduction. However, the oxygen deficiency reduction in thesilicate layer 105-2 progresses even under trace oxygen partialpressure, so that the oxygen partial pressure during the heat treatmentmay be reduced to achieve a condition under which oxidation of theinterface between the base silicon oxide film 103 and the siliconsubstrate 101 is arrested.

This provides a structure in which optimizing process conditions for themetal element diffusion into the base silicon oxide film 103 preventsthe metal elements from reaching the interface between the base siliconoxide film 103 and the silicon substrate 101, as well as provides theinsulating film structure 105 composed of a silicon oxide region 105-1,a silicate region 105-2, and a metal rich region 105-3, as shown in FIG.1D.

As shown in FIG. 2, in metal element concentration distribution in afilm thickness direction, namely, depth direction of the insulating filmstructure 105, metal element concentration is highest on the surface ofthe insulating film structure 105, and decreases with increasing thedepth of the insulating film structure 105, resulting in approximatelyzero of the metal element concentration at a certain depth from thesurface of the insulating film structure 105. More specifically, nometal elements are diffused in a region near the interface with thesilicon substrate 101, so that the metal element concentration issubstantially zero. In other words, in the insulating film structure105, a region near the interface with the silicon substrate 101 getsinto the silicon oxide region 105-1 not containing metal elements. Inthe interface between the insulating film structure 105 and the siliconsubstrate 101, the interface structure as good quality as that providedimmediately after the base silicon oxide film 103 is formed on thesurface of the silicon substrate 101 in a process shown in FIG. 1B canbe maintained. On the other hand, the metallic composition is high in anupper portion of the insulating film structure 105, whereas on thesurface of the insulating film structure 105, a metal oxide notcontaining silicon, or metal rich silicate is determined, depending upona metal diffusion process or a heat treatment condition. The upperregion comprising this metal oxide or metal rich silicate is called themetal rich region 105-3. In the insulating film structure 105, a regionbetween the silicon oxide region 105-1 and the metal rich region 105-3is called the silicate region 105-2. The silicate region 105-2 hascomposition modulation, and the metal element concentration, namely,metallic composition increases and silicon composition decreases ascloser to the metal rich region 105-3, whereas the metal elementconcentration, namely, the metallic composition decreases and thesilicon composition increases as closer to the silicon oxide region105-1. More specifically, the insulating film structure 105 abuts on thesilicon substrate 101, and comprises the following regions: one beingthe silicon oxide region 105-1 into which no metal elements areintroduced by the aforementioned interface reaction, one being acomposition-modulated silicate region 105-2 extending on the siliconoxide region 105-1 and having the composition modulation by introductionof the metal elements associated with the aforementioned interfacereaction, and one being the metal rich silicate region 105-3 extendingon the silicate region 105-2 and having high metal elementconcentration, namely, metallic composition. Note that a gate electrode106 formed on the insulating film structure 105 containing the silicateregion is shown in FIG. 2.

The metal elements supplied onto the surface of the base silicon oxidefilm 103 to form silicate include Zr, Hf, Ta, Al, Ti and Nb, or Sc and Ywhich are rare-earth elements, or La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy,Ho, Er, Tm, Yb, and Lu which are lanthanoid series. A fabrication methodof the high dielectric constant film proposed by the present inventionmay be applied to all of these metal elements, but metal diffusion rateinto the base silicon oxide film 103 varies depending upon thedifference in material properties. For example, a lanthanoid oxiderepresented by La has properties of being likely to mix with a siliconoxide, and the metal diffusion into the base silicon oxide film 103relatively easily progresses. On the other hand, diffusion of Al and thelike into the base silicon oxide film 103 is unlikely to progress, butforms an interface layer from a viewpoint at an atomic level. Inaddition, properties of Zr, Hf, and the like are positioned in themiddle of these properties. Accordingly, it is necessary to optimizemetal supply and diffusion conditions for each of the aforementionedmaterials.

Among these, the film thickness of a metal deposition layer dependent onmetal supply is an important process parameter which determines theproperties of a semiconductor device due to the following reasons. Whenthe film thickness of the metal deposition is thicker than necessary,despite a progress of silicate formation in the interface with the basesilicon oxide film, the metallic composition is high in the upperportion of the metal layer, and in some cases, a thick metal oxide layernot containing silicon is formed. This metal oxide layer not containingsilicon has a high relative dielectric constant, and is effective inreducing leakage current which passes through a gate insulating film,but the thermal stability deteriorates. Furthermore, when fixed chargedensity in the metal oxide is high, a problem involved in thereliability such that device operating voltage shifts occurs. Therefore,in formation of a silicate high dielectric gate insulating filmexcellent in electrical characteristics, it is important to optimize thefilm thickness of the metal deposition layer in addition to optimizationof the aforementioned base oxide film thickness.

In addition, it is preferable that as for diffusion reaction between thebase silicon oxide film and the upper metal layer, all regions of themetal layer 104 react. In the case where unreacted regions are left inthe metal layer 104, characteristic deterioration of the gate insulatingfilm will be caused. In such a case, the unreacted regions in the metallayer 104 may be removed or separated to utilize only regions formed bythe interface reaction with the base silicon oxide film as the gateinsulating film.

FIG. 3A is a longitudinal sectional view showing the insulating filmstructure 105 in which an unreacted region 105-5 is left on the upperportion of the metal layer 104 by the interface reaction between themetal layer 104 and the base silicon oxide film 103 in FIG. 1C. Theinsulating film structure 105 shown in FIG. 3A includes the followingregions: one being the silicon oxide region 105-1 which abuts on thesilicon substrate 101, and into which no metal elements are introducedby the aforementioned interface reaction, one being thecomposition-modulated silicate region 105-2 which extends on the siliconoxide region 105-1, and has the composition modulation by introductionof the metal elements associated with the aforementioned interfacereaction, one being the metal rich silicate region 105-3 which extendson the silicate region 105-2, and has high metal element concentration,namely, metallic composition, and one being an upper unreacted metalregion 105-5 which extends on the metal rich silicate region 105-3. Asdescribed above, the upper unreacted metal region 105-5 causes thecharacteristic deterioration of the gate insulating film, so that theupper unreacted metal region 105-5 is removed, followed by furthercarrying out reforming heat treatment. FIG. 3B is a longitudinalsectional view showing the insulating film structure 105 after the upperunreacted region 105-5 shown in FIG. 3A has been removed, followed byfurther carrying out the reforming heat treatment. The unreacted metalregion 105-5 is capable of being removed, for example, by etching. As awet etching solution, a solution based on a diluted hydrofluoricsolution or an ammonia peroxide solution may be used. Furthermore, thecharacteristics of the gate insulating film may be improved by givingadditional heat treatment subsequent to a process of removing theunreacted metal region 105-5.

In addition, the heat treatment process for implementing the metaldiffusion into the base silicon oxide film 103 from the metal layer 104shown in FIG. 1C is carried out in reducing atmosphere, thereby makingit possible to more effectively implement the diffusion reaction of themetal into the base silicon oxide film 103. This is intended to causeoxygen deficiencies in the aforementioned upper reacted region toaccelerate the metal diffusion into the base silicon oxide film 103 bycarrying out the heat treatment on condition that oxygen atoms are takenfrom the metal diffusion. Hydrogen atmosphere and ammonia atmosphere areeffective as the aforementioned reducing atmosphere. Furthermore, it ispreferable to give the heat treatment in oxygen atmosphere, namely,oxidation treatment subsequent to the treatment in the aforementionedreducing atmosphere to thereby offset the oxygen deficiencies in a metalsilicate film formed by the interface reaction.

In addition, after forming the aforementioned various high dielectricconstant gate insulating films, nitrogen introduction into the films iseffective in improving thermal resistance of the high dielectricconstant film. The aforementioned nitride process includes the heattreatment in ammonia, or nitrogen plasma treatment.

In addition, it is effective to form a cap layer comprising a siliconnitride film with a film thickness of 1.0 nm or less, and preferably 0.5nm or less, or a cap layer comprising a silicon oxynitride film, withthe aim to suppress the interface reaction between a high dielectricconstant insulating film 105 and the gate electrode 106 after formingthe aforementioned various high dielectric constant gate insulatingfilms 105 and before forming the gate electrode 106.

Effective is the gate insulating film structure characterized in that ahigh quality high dielectric constant gate insulating film structure 105has the gate insulating layer 105 with a physical film thickness of 3.5nm or less, which is provided between the silicon substrate 101 and thegate electrode 106, and the physical film thickness of ametal-containing silicate layer present on its upper layer portion isthinner than the film thickness of the base silicon oxide film initiallyformed, and shown in FIG. 1C. FIG. 4 is a diagram for illustrative of arelationship of thicknesses A and B, the thickness A of the metalsilicate region containing metal elements, and the thickness B of thesilicon oxide region not containing metal elements in the gateinsulating film 105. Here, the metal silicate region containing metalelements is equivalent to the composition modulated silicate region105-2 and the metal rich silicate region 105-3 in FIG. 3B, whereas thesilicon oxide region not containing metal elements is equivalent to thesilicon oxide region 105-1 in FIG. 3B. Furthermore, from a viewpoint ofimprovement in the electrical characteristics and reliability of thegate insulating film 105, the thickness A of the metal silicate regionis preferably 1.5 nm or less.

FIG. 5 is a partial longitudinal sectional view showing one example of asemiconductor device to which the insulating film structure according tothe present invention shown in FIG. 2 is applied. A Field EffectTransistor comprises the silicon substrate 101, a source region 109-1and a drain region 109-2 selectively formed in the silicon substrate101, the gate insulating film 105 having the aforementioned insulatingfilm structure formed on the surface of the silicon substrate 101, thegate electrode 106 formed on the gate insulating film 105, nitride filmside walls 107 formed on side walls of the gate electrode 106, and oxidefilm side walls 108 formed on the nitride film side walls 107. Thesilicon nitride film side walls 108 are preferably provided with the aimto protect a gate side wall portion exposed after gate etching.

Furthermore, the aforementioned high dielectric constant gate film ischaracterized in that hysteresis of a gate capacity-gate voltage curveby an applied bias within the device operating voltage is 5 mV or less.

In addition, the aforementioned description has indicated a process offorming the metal layer which is to be a metal diffusion source, on thebase silicon oxide film to heat-treat this laminated structure assilicate formation using the interface reaction between the siliconoxide film and the metal layer. However, it is also possible that afterforming the metal layer on the base silicon oxide film, an upper caplayer is further formed on the metal layer, and then the heat treatmentis given to cause the metal diffusion from the metal layer into theupper cap layer and the base silicon oxide film, both of which are aboveand under the metal layer, to form the metal silicate gate insulatingfilm having the component modulation.

FIG. 6A to 6D are partial longitudinal sectional views in themanufacturing process of the insulating film structure comprising thesilicate high dielectric constant thin film included in a semiconductordevice in another embodiment according to the present invention.

As shown in FIG. 6A, the base silicon oxide film 103 is formed on thesilicon substrate 101. As shown in FIG. 6B, the metal elements aresupplied onto the surface of the base silicon oxide film 103 to form themetal layer 104. As shown in FIG. 6C, a cap layer 110 is formed on themetal layer 104. As shown in FIG. 6D, the insulating film structure 105including the silicate region is formed on the silicon substrate 101 bythe heat treatment. A high dielectric constant film layer comprisingsilicate is not directly deposited on the silicon substrate 101, but themetal is thermally diffused from the metal layer 104 into the basesilicon oxide film 103 and the cap layer 110 to form the insulating filmstructure 105 including the silicate region shown in FIG. 6D by allowingthe heat treatment to cause the silicate reaction in the interfacebetween the base silicon oxide film 103 and the metal layer 104 and inthe interface between the cap layer 110 and the metal layer 104. Aninsulating film structure 105′ may be selected from the followingregions: one being the silicon oxide region 105-1 which extends on thesilicon substrate 101, and into which no metal elements are introduced,one being a first silicate region 105-2 which extends on the siliconoxide region 105-1 and into which the metal elements are thermallydiffused by the aforementioned silicate reaction, one being the metalrich region 105-3 which extends on the first silicate region 105-2, andone being a second silicate region 105-4 which extends on the metal richregion 105-3, and into which the metal elements are thermally diffusedby the aforementioned silicate reaction. The aforementioned base siliconoxide film 103 may be selected from a combination of a silicon oxidefilm and a silicon oxynitride film. The cap layer 110 may be selectedfrom the combinations of a silicon layer, a silicon oxide film layer, asilicon nitride layer, and a silicon oxynitride film layer. Furthermore,it is effective to use ultra-thin films of 1 nm or less, preferably 0.5nm or less as the film thickness of the cap layer 110. Note that thedescription overlapped with the aforementioned manufacturing processreferring to FIG. 1A to FIG. 1D will be omitted to avoid redundancy.

FIG. 7 is a diagram showing the metal element concentration distributionin the film thickness direction of the silicate high dielectric constantthin film included in the insulating film structure 105′ shown in FIG.6D. As shown in FIG. 7, for the metal element concentration distributionin the film thickness direction, namely, the depth direction of theinsulating film structure 105′, the metal element concentration ishighest in the metal rich region 105-3, and decreases with increasingthe distance from the metal rich region 105-3 in the first and secondsilicate regions 105-2 and 105-4. More specifically, in the firstsilicate region 105-2, the metal element concentration decreases withincreasing the depth, whereas in the second silicate region 105-4, themetal element concentration increases with increasing the depth. Thatis, in a region close to the interface with the silicon substrate 101,no metal elements are diffused, so that the metal element concentrationis substantially zero. Namely, in the insulating film structure 105′,the region close to the interface with the silicon substrate 101 is thesilicon oxide region 105-1 not containing metal elements.

EXAMPLES First Example

FIG. 8A to FIG. 8D are longitudinal sectional views showing amanufacturing process of a lanthanum silicate high dielectric constantthin film included in a semiconductor device in a first exampleaccording to the present invention. FIG. 9 is a diagram showing anoverview of constitution of vacuum evaporation apparatus used formanufacturing the lanthanum silicate high dielectric constant thin filmshown in FIG. 8A to FIG. 8D. FIG. 10 is a diagram showing a relationshipbetween Equivalent Oxide Thickness and leakage current which are foundfrom capacity-voltage characteristics and current-voltagecharacteristics of the lanthanum silicate high dielectric constant thinfilm shown in FIG. 8D.

In the first example, a base silicon oxide film 103 was formed as a baselayer, a lanthanum silicate high dielectric constant thin film 205 wasformed using La as a metal element, and characteristics of thesemiconductor device were verified using the lanthanum silicate highdielectric constant thin film 205.

As shown in FIG. 8A, after cleaning of a silicon substrate 101, asurface oxide film was removed with hydrofluoric acid treatment, and thesilicon substrate 101 was surface-oxidized by RTO to form the basesilicon oxide film 103 with a film thickness of 1.1 nm. The RTO wascarried out by making a substrate temperature 700° C. under reducedpressure oxygen conditions (500 Pa).

Next, the silicon substrate 101 in which the base silicon oxide film 103was formed was mounted on a wafer transportation system 403, and wasintroduced into a deposition chamber 401 through a wafer introductionchamber 402 to deposit a metal lanthanum layer 204 on the base siliconoxide film 103 by electron beam heating (electron-beam evaporation) ofan LA evaporation source using an electron beam evaporation mechanism406. During deposition of metal elements, a degree of vacuum of thedeposition chamber 401 was set to a condition of 2×10−9 Torr or less byvacuuming with a roughing vacuum pump 408 and a main air pump 407, and asubstrate temperature of the silicon substrate 101 was set to 500° C. byroom temperature and heating of a substrate heating mechanism 405.

Next, the silicon substrate 101 on which the metal lanthanum layer 204was deposited was taken out of the deposition chamber 401, and the heattreatment was carried out in nitrogen atmosphere at 500° C. for 10minutes for the sake of compensation for oxygen deficiencies in the filmto form the lanthanum silicate high dielectric constant thin film 205composed of a silicon oxide film region 205-1, an La silicate region205-2, and an La rich region 205-3. A heat treatment process may becarried out using a horizontal quartz reactor to cause oxygenintroduction into a film and metal diffusion into the base silicon oxidefilm 103 by means of residual oxygen in treatment atmosphere oradsorption oxygen in wafer transportation.

With respect to the lanthanum silicate high dielectric constant thinfilm 205 formed in this way, capacity-voltage and current-voltagecharacteristics were evaluated, and Equivalent Oxide Thickness (EOT) andleakage current (Jg) were measured, which was compared with thecharacteristics of the base silicon oxide film 103. The comparisonresult is shown in FIG. 10.

FIG. 10 shows respective characteristic results of samples subjected tocomparison under different conditions that a temperature of the siliconsubstrate 101 during lanthanum deposition was room temperature and 500°C., which reveals that the leakage current is reduced in all thesamples, as compared with the base silicon oxide film 103.

In addition, the samples subjected to the comparison carried out bymaking the temperature of the silicon substrate 101 a temperature of500° C. during the lanthanum deposition showed that the Equivalent OxideThickness was thinner than the film thickness of the base silicon oxidefilm 103, from which it was confirmed that lanthanum was diffused intothe base silicon oxide film 103, and high dielectricity advanced by theaforementioned manufacturing method of the present invention.Furthermore, the thinnest sample of the Equivalent Oxide Thickness amongthe samples subjected to the comparison carried out by making thetemperature of the silicon substrate 101 room temperature during thelanthanum deposition showed that the Equivalent Oxide Thickness wasthinner than the film thickness of the base silicon oxide film 103, fromwhich it was confirmed that the high dielectricity by metal diffusionadvanced even on condition that the temperature of the silicon substrate101 was room temperature. In this way, the Equivalent Oxide Thicknesshad a tendency to be thin in the samples whose substrate temperaturesare high during the lanthanum deposition, whereby effects in providingtemperature rise to the silicon substrate 101 during the lanthanumdeposition were confirmed.

In addition, as a result of having measured interface state density, itwas confirmed that defect density was reduced to ⅕ to 1/10 by applyingthe manufacturing method of the present invention, as compared with thecase where the lanthanum silicate was directly deposited on the siliconsubstrate 101. Furthermore, as a result of having made the lanthanumsilicate high dielectric constant thin film 205 a gate insulating filmto prototype the MOSFET using a polysilicon gate electrode, the mobilityincreased by not less than 50%, as compared with the case where thelanthanum silicate was directly deposited on the silicon substrate 101.

Second Example

FIG. 11A to FIG. 11D are longitudinal sectional views showing amanufacturing process of a hafnium silicate high dielectric constantthin film included in a semiconductor device of a second exampleaccording to the present invention. FIG. 12 is a diagram showing anoverview of constitution of sputter deposition apparatus used for themanufacturing process of the hafnium silicate high dielectric constantthin film shown in FIG. 11A to FIG. 11D.

In the second example, a silicon oxynitride film 203 was formed as abase layer, and a hafnium silicate high dielectric constant thin film305 was formed using Hf as a metal element, the hafnium silicate highdielectric constant thin film 305 being used to verify characteristicsof a semiconductor device. The reason for which the silicon oxynitridefilm 203 was used as a base oxide film in the second example was for thesake of improvement in thermal resistance by addition of nitrogen tohigh dielectric constant materials.

After cleaning of a silicon substrate 101, a surface oxide film wasremoved with hydrofluoric acid treatment to surface-oxidize the siliconsubstrate 101 by RTO, forming a base silicon oxide film 103 with a filmthickness of 1.5 nm. The RTO was carried out by making a substratetemperature 700° C. under reduced pressure oxygen conditions (500 Pa).

Next, nitride treatment for a surface of the base silicon oxide film 103was carried out by means of vacuum apparatus on which an ECR (ElectronCyclotron Resonance) radical source was mounted as a plasma source toform the silicon oxynitride film 203. The nitride treatment was carriedout under irradiation conditions of nitrogen radical at a substratetemperature of 500° C., nitrogen pressure of 0.3 Pa, and input power of100 W.

Next, the silicon substrate 101 in which the silicon oxynitride film 203was formed was mounted on a wafer transportation system 703, andintroduced into a deposition chamber 701, which was ultrahighvacuum-enabled remote type of sputter apparatus, through a waferintroduction chamber 702. A sputter evaporation mechanism 706 was thenused to carry out metal layer deposition making an Hf target evaporationsource and argon sputter gas to deposit an hafnium deposition layer 304on the silicon oxynitride film 203. During deposition of metal elements,a degree of vacuum of the deposition chamber 701 was set to a conditionof 5×10−9 Torr or less by vacuuming with a roughing vacuum pump 708 anda main air pump 707, the substrate temperature of the silicon substrate101 was set to room temperature, distance between a sputter source and awafer was set to 300 mm for reducing damage, argon gas partial pressurewas set to 0.05 Pa, and input power was set to 500 W.

Next, after the deposition of the hafnium deposition layer 304,continuous heat treatment was carried out at the degree of vacuum of1×10⁻⁶ Torr or less at 600° C. for 10 minutes, and then the siliconsubstrate 101 was taken out of the deposition chamber 701. The heattreatment was further carried out in nitrogen atmosphere at 500° C. for10 minutes for the sake of compensation for oxygen deficiencies in afilm to form the hafnium silicate high dielectric constant thin film 305composed of a silicon oxynitride film region 305-1, an Hf silicateregion 305-2, and an Hf rich region 305-3. A heat treatment process maybe carried out using a horizontal quartz reactor to allow residualoxygen in treatment atmosphere, or adsorption oxygen in wafertransportation to cause oxygen introduction into a film and metaldiffusion into the base silicon oxide film 103.

As a result of evaluation of capacity-voltage and current-voltagecharacteristics, it was confirmed that Effective Oxide Thickness was1.45 nm, and that leakage current was capable of being reduced by threeto four digits more than that of a silicon oxide film.

In addition, it was confirmed that the manufacturing method of thepresent invention was applied to thereby reduce interface defect densityby approximately 1/5, as compared with the case where HfO₂ was directlydeposited on the base silicon oxide film 103 having a thickness of 0.5nm by a reactive sputtering method in accordance with the prior art.Furthermore, as a result of having evaluated heattreatment-crystallization temperature by the heat treatment, thermalresistance was improved by 50° C. to 100° C. with respect to the hafniumsilicate high dielectric constant thin film 305 into which nitrogen wasnot introduced. On the other hand, as a result of having made thehafnium silicate high dielectric constant thin film 305 a gateinsulating film to prototype the MOSFET using a polysilicon gateelectrode, the mobility increased by not less than 40%, as compared withthe case where the hafnium silicate was directly deposited on thesilicon substrate.

In the present second example, it was confirmed that when the MOSFET wasfabricated by making a deposited film thickness of metallic hafnium 0.4to 0.6 nm and 1.0 nm, leakage current values could be reduced byapproximately three digits and approximately four digits, respectively,as compared with the silicon oxide film.

In addition, the life of a device (insulating film reliability)estimated from electrical defects (interface defect density: Dit)present in an interface between an insulating film and a siliconsubstrate, and a threshold voltage shift associated with deviceoperation was evaluated for these devices with different filmthicknesses of metallic hafnium. As a result, it was confirmed that in adevice fabricated by making the film thickness of metallic Hf 0.4 to 0.6nm, the interface defect density could be reduced to less than ½, ascompared with the one fabricated by making the film thickness ofdeposition 1.0 nm, and that the life of a device (reliability) could beimproved ten times or more. Furthermore, it was confirmed thathysteresis of capacity-gate voltage characteristics (C-Vcharacteristics) within operating voltage of a transistor was 5 mV orless. Accordingly, it was confirmed that from a viewpoint of reducedleakage current and device reliability such as device life, the filmthickness of the metal layer was preferably 1 nm or less, and morepreferably 0.6 nm or less. The lower limit of the film thickness is notparticularly limited as far as a silicate layer having a significantthickness is formed, but the effect is noticeable when the filmthickness is, for example, not less than 0.4 nm. In making devicedesign, any film thickness may be selected from such a film thicknessrange. However, for example, if priority is given to reduced leakagecurrent, silicate deposition making the thickness of a metal depositionlayer a value close to 1 nm is effective. On the other hand, if thepriority is given to the device reliability, the silicate depositionmaking the thickness of the metal deposition layer 0.4 to 0.6 nm iseffective.

In addition, it was confirmed that a typical structure of a gateinsulating film achieving an effect of reducing the leakage current ofthe gate insulating film and improvement in transistor mobility, as wellas ensuring of the reliability had a gross physical film thickness of3.5 nm or less, and that if a physical film thickness of a base siliconoxide film region (B) not containing metal elements was thicker than thephysical film thickness of a silicate region containing metal elements,namely, if a relationship of A<B was satisfied, excellentcharacteristics could be obtained. The typical example included thephysical film thickness of an unreacted base silicon oxide film of 1.4nm, the physical film thickness of a metal-containing upper silicatelayer of 1.2 nm, and an electrical film thickness of 1.75 nm.

Furthermore, for fabrication of the aforementioned transistor structure,a small transistor with a short gate length provided favorabletransistor characteristics, when a side wall comprising a siliconnitride film was formed on a gate side wall.

In addition, Hf metal was used as a metal diffusion source in theaforementioned examples, but it is useful to introduce nitrogen assputtering gas during metal Hf deposition to deposit HfN (hafniumnitride). An Hf silicate film (HfSiON) was able to be fabricated bygiving the heat treatment onto the base silicon oxide film with athickness of 1.5 nm after deposition of HfN in a manner similar to theforegoing. Nitrogen remains as little as approximately 4% in the Hfsilicate film because part of nitrogen in a film was thermally desorbedduring the heat treatment. However, it was confirmed that nitrogen wasintroduced into metal silicate by the present deposition method, therebymaking it possible to increase the crystallization temperature of theinsulating film by 50° C., with improvement in thermal resistance bynitrogen introduction. Additionally, in the case of a metal nitride,from a viewpoint of ensuring of the reliability over the gate insulatingfilm, when the film thickness of a metal nitride film was 1 nm or less,and preferably 0.6 nm or less, the hysteresis of capacity-gate voltagecharacteristics of the gate insulating film was able to be 5 mV.

As has been described hereinbefore, according to the present embodiment,after forming the base silicon oxide film 103 on a surface of thesilicon substrate 101, a metal layer deposition process and the heattreatment process of supplying metal elements which constitute a highdielectric constant film on a surface of the base silicon oxide film 103allow the metal elements to be diffused into the base silicon oxide film103 to thereby form an insulating film structure 105 including thesilicate region as the gate insulating film, thereby enabling formationof a gate insulating film structure having a good quality interfacebetween the base silicon oxide film and the silicon substrate in theinterface between the high dielectric constant thin film and the siliconsubstrate, with an effect that improvement in interface electricalcharacteristics, which has been a longstanding task in practical use ofthe high dielectric constant thin film may be achieved.

Furthermore, according to the present embodiment, independent control ofthe metal diffusion into the base silicon oxide film 103 allows themetal elements to be diffused only onto the surface side of the basesilicon oxide film 103, making it easier to optimize conditions that nometal elements reach the interface between a silicon oxide film and thesilicon substrate, with an effect that fabrication of the highdielectric gate insulating film having excellent interface electricalcharacteristics is enabled.

In these and other embodiments, the film thickness of metal is thinned,and the metal film is completely diffused and made into silicate toachieve silicate deposition. However, if the metal film having arelatively thick film thickness is used, there is a possibility that anunreacted metal region with the base silicon oxide film could remainafter the heat treatment. In this case, the unreacted metal region maybe removed to use only a region made into silicate as the gateinsulating film.

In addition, although the aforementioned first and second examples showthe case where a bilayer structure of the base oxide film and the uppermetal-containing layer has been used, a silicon or silicon oxide filmbased cap layer is further formed above the aforementioned bilayerstructure before giving the heat treatment, thereby making it possibleto form a structure having a silicon rich region on the uppermost layer.

In this case, a silicon cap layer with a film thickness of 0.5 nm wasformed by the sputter deposition using an Si target, after the bilayerstructure comprising the silicon oxide film and metal Hf had been formedby RTO and sputter deposition similar to those of the second example.Then, treatment was carried out in oxygen atmosphere at 500° C. for twominutes, followed by giving the heat treatment in nitrogen at 900° C.The heat treatment runs formation of a surface silicon oxide film layerby oxidation of a surface silicon cap layer in parallel with the metaldiffusion from a metal Hf layer into upper and lower silicon oxidelayers to form the silicate layer.

Component distribution in a thickness direction of this silicate layeris high in the lowermost portion abutting on an upper portion of thefilm and the silicon substrate, and low in the central portion (aportion in which the metal layer was initially formed). In contrast withthis, metallic (Hf) composition indicates a maximal value in thevicinity of the central portion of the film, and the Hf compositiondecreases as closer to a silicon interface and the uppermost portion.Namely, a structure provided with the component distribution has beenprovided. Additionally, as applications of the aforementioned depositionmethods, use of the silicon oxide film, the silicon oxynitride film, andthe silicon nitride film as a surface cap layer, and further the use ofa metal silicate layer, a metal aluminate layer, a metal oxide layer,and a metal nitride layer as the metal diffusion source were found to beeffective.

In the semiconductor device, its manufacturing method, and itsmanufacturing apparatus of the present invention, after forming the basesilicon oxide film on the surface of the silicon substrate, the metallayer deposition process and the heat treatment process of supplyingmetal elements which constitute the high dielectric constant film on thesurface of the silicon oxide film allow the metal elements to bediffused into the silicon oxide film to thereby form the silicate layeras the gate insulating film, thereby enabling formation of the gateinsulating film structure having a good quality interface between thesilicon oxide film and the silicon substrate in the interface betweenthe high dielectric constant thin film and the silicon substrate, withan effect that improvement in interface electrical characteristics,which has been a longstanding task in practical use of the highdielectric constant insulating film may be achieved.

Furthermore, in the semiconductor device, its manufacturing method, andits manufacturing apparatus of the present invention, independentcontrol of the metal diffusion into the silicon oxide film allows themetal elements to be diffused only onto the surface side of the siliconoxide film, making it easier to optimize the conditions that no metalelements reach the interface between the silicon oxide film and thesilicon substrate, with an effect that the fabrication of the highdielectric constant gate insulating film having excellent interfaceelectrical characteristics is enabled.

Note that the number, position, shape and the like of the aforementionedconstituent members are not limited to the aforementioned embodiments,and preferred number, position, shape, and the like may be allowed inimplementing the present invention. Note that in each figure, the samenumerals are given to the same components.

INDUSTRIAL APPLICABILITY

Furthermore, application of the present invention is not limited tospecific devices described in the aforementioned examples, as far as asemiconductor device including an insulating film structure whichelectrically insulates a conductive region from a silicon region isconcerned.

In addition, the insulating film structure is not limited to a gateinsulating film, and the semiconductor device includes one whichelectrically insulates the conductive region from the silicon region.

While the present invention has been described by linking to somepreferred embodiments and examples, it is to be understood that theseembodiments and examples are merely illustrative of the presentinvention with practical examples and not restrictive. While it will beobvious to those skilled in the art that various changes andsubstitutions by equivalent components and techniques are eased, uponreading the specification, it is believed obvious that such changes andsubstitutions are included in the true scope and spirit of theaccompanying claims.

1. A semiconductor device comprising an insulating film structure whichelectrically insulates a conductive region from a silicon region,wherein said insulating film structure extends on said silicon regionand under said conductive region, said insulating film structure furthercomprising at least one silicate region composed of a silicon oxidecontaining at least one metal element thermally diffused.
 2. Thesemiconductor device according to claim 1, wherein concentrationdistribution of said at least one metal element in said silicate regionis distribution derived from thermal diffusion.
 3. The semiconductordevice according to claim 1, wherein said insulating film structurecomprises at least one silicon oxide region composed of a silicon oxidenot containing said at least one metal element, at least one metal richregion having high concentration of said at least one metal element, andsaid at least one silicate region which is located between said siliconoxide region and said metal rich region and has lower concentration ofsaid at least one metal element than that of said metal rich region. 4.The semiconductor device according to claim 1, wherein said silicateregion has composition modulation in which composition of said at leastone metal element increases as closer to said metal rich region anddecreases as closer to said silicon oxide region, and, on the otherhand, in which the composition of silicon decreases as closer to saidmetal rich region and increases as closer to said silicon oxide region.5. The semiconductor device according to claim 3, wherein said metalrich region comprises a metal oxide not containing silicon.
 6. Thesemiconductor device according to claim 3, wherein said metal richregion comprises metal rich silicate having higher concentrationdistribution of said at least one metal element than that of saidsilicate region.
 7. The semiconductor device according to claim 3,wherein said silicon oxide region is located on said silicon region,said silicate region being located on said silicon oxide region, saidmetal rich region being located on said silicate region.
 8. Thesemiconductor device according to claim 7, wherein said silicate regionhas composition modulation in which composition of said at least onemetal element increases toward a surface of the device, and thecomposition of silicon decreases toward the surface of the device. 9.The semiconductor device according to claim 8, wherein a second silicateregion further extends on said metal rich region, the second silicateregion having composition modulation in which composition of said atleast one metal element decreases upward, and the composition of siliconincreases upward.
 10. The semiconductor device according to claim 1,wherein said silicon region comprises a silicon substrate, saidconductive region comprises a gate electrode, and said insulating filmstructure comprises a gate insulating film.
 11. The semiconductor deviceaccording to claim 1, wherein said at least one metal element is atleast any one selected from a group of Zr, Hf, Ta, Al, Ti, Nb, Sc, Y,La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.
 12. Thesemiconductor device according to claim 1, wherein a source of said atleast one metal element subjected to thermal diffusion comprises a metallayer deposited on a surface of a base silicon oxide film extending onsaid silicon region in atmosphere with residual oxygen partial pressureof 1×10⁻⁶ Torr or less.
 13. The semiconductor device according to claim1, wherein a source of said at least one metal element subjected tothermal diffusion comprises a metal layer deposited on a surface of abase silicon oxide film extending on said silicon-region by causingtemperature rise of said silicon region from room temperature.
 14. Thesemiconductor device according to claim 1, wherein a source of said atleast one metal element subjected to thermal diffusion comprises a metallayer having a film thickness of 1 nm or less.
 15. The semiconductordevice according to claim 1, wherein a source of said at least one metalelement subjected to thermal diffusion comprises a metal layer having afilm thickness of 0.6 nm or less.
 16. The semiconductor device accordingto claim 1, wherein said at least one metal element is only Al, and asource of the metal element comprises a metal layer abutting on asurface of a base silicon oxide film having a film thickness of not lessthan 0.6 nm, which extends on said silicon region.
 17. The semiconductordevice according to claim 1, wherein said at least one metal elementcomprises at least only any one selected from a group of Zr, Hf, Ta, Al,Ti, Nb, Sc, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, andLu, and a source of the metal element comprises a metal layer abuttingon a surface of a base silicon oxide film having a film thickness of notless than 1 nm, which extends on said silicon region.
 18. Thesemiconductor device according to claim 1, wherein said insulating filmstructure up to and including its uppermost portion is composed ofsilicate containing said at least one metal element subjected to thermaldiffusion.
 19. The semiconductor device according to claim 1, whereinsaid insulating film structure does not include an unreacted metalregion not containing silicon.
 20. The semiconductor device according toclaim 19, wherein said unreacted metal region comprises a region whichis removed by at least any one of a hydrofluoric acid solution and anammonia peroxide solution.
 21. The semiconductor device according toclaim 19, wherein said insulating film structure has film qualityreformed as a result of heat treatment in a state where said unreactedmetal region is not present.
 22. The semiconductor device according toclaim 1, wherein said insulating film structure at least comprises afirst silicate region composed of a silicon oxide containing at leastone metal element thermally diffused, and a second silicate region whichis located above the first silicate region and is composed of asilicon-containing insulator containing said at least one metal elementthermally diffused.
 23. The semiconductor device according to claim 22,wherein said silicon-containing insulator comprises any one of a siliconoxide film, a silicon oxynitride film, a silicon nitride film, and atleast two laminated structures of these.
 24. The semiconductor deviceaccording to claim 22, wherein said first silicate region comprises abase silicon oxide film containing said at least one metal elementsubjected to thermal treatment from a metal layer abutting on an uppersurface, and wherein said second silicate region comprises a cap layerof a silicon-containing insulator containing said at least one metalelement thermally diffused from said metal layer abutting on a lowersurface.
 25. The semiconductor device according to claim 24, wherein afilm thickness of said cap layer is 1 nm or less.
 26. The semiconductordevice according to claims 24, wherein a film thickness of said caplayer is 0.5 nm or less.
 27. The semiconductor device according to claim22, wherein said insulating film structure has composition modulation inwhich composition of silicon in a film thickness direction is high inthe lowermost portion and uppermost portion and low in the centralposition, in the vicinity of said silicon region.
 28. The semiconductordevice according to claim 22, wherein said insulating film structure hascomposition modulation in which composition of said at least one metalelement in a film thickness direction is low in the lowermost portionand uppermost portion, which are located in the vicinity of said siliconregion, and high in the central portion.
 29. The semiconductor deviceaccording to claim 1, wherein an Equivalent Oxide Thickness of saidinsulating film structure is smaller than the Equivalent Oxide Thicknessof a silicon oxide film into which said at least one metal element isdiffused.
 30. The semiconductor device according to claim 1, whereinsaid silicon oxide constituting said at least one silicate region is asilicon oxynitride into which nitrogen is introduced.
 31. Thesemiconductor device according to claim 1, wherein concentrationdistribution of said at least one metal element in said at least onesilicate region is a distribution derived from heat treatment underreduced oxygen pressure conditions below atmospheric pressure.
 32. Thesemiconductor device according to claim 1, wherein said insulating filmstructure further comprises a cap region composed of any one of asilicon nitride and a silicon oxynitride on said at least one silicateregion.
 33. The semiconductor device according to claim 32, wherein athickness of said cap region is 0.5 nm or less.
 34. The semiconductordevice according to claim 1, wherein said conductive region comprises agate electrode, and said insulating film structure comprises a gateinsulating film, and wherein a hysteresis width of C-V characteristicsis 5 mV or less for a gate bias within device operating voltage.
 35. Thesemiconductor device according to claim 1, wherein said insulating filmstructure comprises said silicate region composed of a silicon oxidecontaining said at least one metal element, and a silicon oxide regioncomposed of a silicon oxide not containing a metal element, wherein aphysical film thickness of said insulating film structure is 3.5 nm orless, and a physical thickness of said silicate region is thinner thanthe physical thickness of said silicon oxide region.
 36. Thesemiconductor device according to claim 35, wherein a physical thicknessof said silicate region is 1.5 nm or less.
 37. The semiconductor deviceaccording to claim 35, wherein said conductive region comprises a gateelectrode, said insulating film structure comprises a gate insulatingfilm, and the gate electrode has nitride film side walls.
 38. Amanufacturing method of a semiconductor device comprising an insulatingfilm structure which electrically insulates a conductive region from asilicon region, wherein the manufacturing method further comprising atleast steps of: forming a base silicon oxide film on said siliconregion; forming a metal layer on said base silicon oxide film; andforming the insulating film structure, wherein the insulating filmstructure is formed by giving heat treatment to cause a silicatereaction in an interface between said base silicon oxide film and saidmetal layer to allow thermal diffusion of at least one metal elementcontained in said metal layer into said base silicon oxide film tothereby form the insulating film structure including a silicate regioncomposed of a silicon oxide containing said at least one metal elementthermally diffused in a region of at least part of said base siliconoxide film.
 39. The manufacturing method of a semiconductor deviceaccording to claim 38, wherein said heat treatment causing saidinterface silicate reaction is carried out in reducing atmosphere. 40.The manufacturing method of a semiconductor device according to claim38, wherein said heat treatment causing said interface silicate reactionis carried out in atmosphere containing any one of hydrogen and ammonia.41. The manufacturing method of a semiconductor device according toclaim 38, wherein said thermal diffusion forms said insulating filmstructure comprising at least one silicon oxide region composed of asilicon oxide into which said at least one metal element is notdiffused, at least one metal rich region into which said at least onemetal element has been diffused at high concentration, and said at leastone silicate region which is located between said silicon oxide regionand said metal rich region, and into which said at least one metalelement has been diffused at concentration lower than that of said metalrich region.
 42. The manufacturing method of a semiconductor deviceaccording to claim 41, wherein said silicate region has compositionmodulation in which composition of said at least one metal elementincreases as closer to said metal rich region and decreases as closer tosaid silicon oxide region, and, on the other hand, in which thecomposition of silicon decreases as closer to said metal rich region andincreases as closer to said silicon oxide region.
 43. The manufacturingmethod of a semiconductor device according to claim 41, wherein saidmetal rich region comprises a metal oxide not containing silicon. 44.The manufacturing method of a semiconductor device according to claim41, wherein said metal rich region comprises metal rich silicate havinghigher concentration distribution of said at least one metal elementthan that of said silicate region.
 45. The manufacturing method of asemiconductor device according to claim 38, wherein a process of formingsaid metal layer comprises a deposition process carried out by settingresidual oxygen partial pressure in treatment atmosphere to 1×10⁻⁶ Torror less.
 46. The manufacturing method of a semiconductor deviceaccording to claim 38, wherein a deposition process of said metal layeris carried out by causing temperature rise of said silicon region fromroom temperature.
 47. The manufacturing method of a semiconductor deviceaccording to claim 38, wherein a nitrization process is further carriedout subsequent to said heat treatment process.
 48. The manufacturingmethod of a semiconductor device according to claim 47, wherein saidnitrization process comprises heat treatment in ammonia.
 49. Themanufacturing method of a semiconductor device according to claim 47,wherein said nitride treatment process comprises nitrogen plasmatreatment.
 50. The manufacturing method of a semiconductor deviceaccording to claim 38, wherein said at least one metal element is atleast any one selected from a group of Zr, Hf, Ta, Al, Ti, Nb, Sc, Y,La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.
 51. Themanufacturing method of a semiconductor device according to claim 38,wherein said at least one metal element is only Al, and said basesilicon oxide film is formed with a film thickness of not less than 0.6nm.
 52. The manufacturing method of a semiconductor device according toclaim 38, wherein said at least one metal element contains at least anyone selected from a group of Zr, Hf, Ta, Al, Ti, Nb, Sc, Y, La, Ce, Pr,Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and said base siliconoxide film is formed with a film thickness of not less than 1 nm. 53.The manufacturing method of a semiconductor device according to claim38, wherein a forming process of said metal layer is carried out oncondition that a film thickness of metal deposition is 1 nm or less. 54.The manufacturing method of a semiconductor device according to claim38, wherein a forming process of said metal layer is a process carriedout on condition that a film thickness of metal deposition is 0.6 nm orless.
 55. The manufacturing method of a semiconductor device accordingto claim 38, wherein said heat treatment process is carried out for asilicate reaction in an interface between said metal layer and said basesilicon oxide film to progress to an upper portion of said metal layer,thereby forming said insulating film structure up to and including itsuppermost portion from silicate.
 56. The manufacturing method of asemiconductor device according to claim 38, the manufacturing methodfurther comprising a step of: removing an unreacted metal regionsubsequent to said heat treatment process, when the unreacted metalregion is left in said metal layer by said heat treatment process. 57.The manufacturing method of a semiconductor device according to claim56, wherein a process of removing said unreacted metal region is carriedout by use of a hydrofluoric acid solution or an ammonia peroxidesolution.
 58. The manufacturing method of a semiconductor deviceaccording to claim 56, further comprising a heat treatment process forreforming film quality subsequent to a process of removing saidunreacted metal region.
 59. The manufacturing method of a semiconductordevice according to claim 38, the manufacturing method furthercomprising a step of: depositing a cap layer composed of asilicon-containing insulating film on said metal layer after a formationprocess of said metal layer and before said heat treatment process tothereby allow said silicate reaction to cause thermal diffusion of saidat least one metal element into said base silicon oxide film and saidcap layer to thereby form a first silicate layer composed of a siliconoxide containing said at least one metal element thermally diffused in aregion of at least part of said base silicon oxide film, as well as toform a second silicate layer composed of a silicon insulator containingsaid at least one metal layer thermally diffused in a region of at leastpart of said cap layer.
 60. The manufacturing method of a semiconductordevice according to claim 59, wherein said cap layer comprises any oneselected from a group of a silicon oxide film, a silicon oxynitridefilm, a silicon nitride film, and a laminated structure of at least twofrom the silicon oxide film, the silicon oxynitride film, and thesilicon nitride film.
 61. The manufacturing method of a semiconductordevice according to claim 59, wherein a film thickness of said cap layeris 1 nm or less.
 62. The manufacturing method of a semiconductor deviceaccording to claim 59, wherein a film thickness of said cap layer is 0.5nm or less.
 63. The manufacturing method of a semiconductor deviceaccording to claim 38, wherein said insulating film structure hascomposition modulation in which composition of silicon in a filmthickness direction is high in the lowermost portion and uppermostportion, which are located in the vicinity of said silicon region, andlow in the central portion.
 64. The manufacturing method of asemiconductor device according to claim 38, wherein said insulating filmstructure has composition modulation in which composition of said atleast one metal element in a film thickness direction is low in thelowermost portion and uppermost portion, which are located in thevicinity of said silicon region, and high in the central portion. 65.The manufacturing method of a semiconductor device according to claim38, wherein an Equivalent Oxide Thickness of said insulating filmstructure is smaller than the Equivalent Oxide Thickness of said basesilicon oxide film.
 66. The manufacturing method of a semiconductordevice according to claim 38, wherein said base silicon oxide filmcomprises a silicon oxynitride film into which nitrogen is introduced.67. The manufacturing method of a semiconductor device according toclaim 38, wherein said heat treatment process is carried out underreduced oxygen pressure conditions below atmospheric pressure.
 68. Themanufacturing method of a semiconductor device according to claim 38,wherein said silicon region comprises a silicon substrate, saidconductive region comprises a gate electrode, and said insulating filmstructure comprises a gate insulating film.
 69. (canceled) 70.(canceled)
 71. (canceled)